Shading Compilers

Graphics hardware evolution in the past year has been highlighted by improved shading resources, the introduction of dynamic flow control and the emergence of multi-GPU system configurations. Executed program length increased substantially and register availability became more affordable. As a result, compiler support for segmenting a shading program to fit hardware constraints has diminished and is mostly required on low cost hardware platforms. The presence of dynamic flow control functionality has made true loops and conditionals, nested or un-nested, first class citizens in a shader description. Dynamic branching brings speed-ups to many algorithms that contain early out opportunities, while also simplifying shader programmability. Data dependent flow control might first be looked at odds with the SIMD architecture nature of the GPU. Nonlinear flow control usually results in poor efficiency manifested by idling internal processors and other resources. Shading compilers however have been alleviating these shortfalls by transforming data dependent structures into linear flow control nodes operating on large data sets. Finally, multi-GPU load partition schemes are now in place to better address performance scalability in several application domains. Both image and time distribution methods have been deployed and leverage of the significant high bandwidth of the relatively newly introduced PCI-Express® [PCIExpress 2004] bus architecture.